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IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 32-BIT BUFFER/ DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in 96-ball LFBGA package
IDT74ALVCH32244
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for Heavy Loads
This 32-bit buffer/driver is built using advanced dual metal CMOS technology. This high-speed, low power device offers bus/backplane interface capability with improved packing density. The device has a flowthrough organization for simplifying board layout. The three-state controls operate this device in a Quad-Nibble, Dual-Byte or single 16-bit word mode. All inputs are designed with hysteresis for improved noise margin. The ALVCH32244 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH32244 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
A3 1OE 1A1 1A2 1A3 1A4 A5 A2 A1 B2 B1 1Y1 1Y2 1Y3 1Y4
3OE
H4 5OE E5 E2 3Y1 E1 F2 F1 5A1 5A2 5A3 5A4
J3 7OE J5 J6 K5 K6 J2 J1 K2 K1 5Y1 5Y2 5Y3 5Y4
T4
N5 7A1 N6 7A2 P5 7A3 7A4 P6
N2 N1 P2 P1
3A1 E6 3A2 F5 3A3 3A4 F6
7Y1
A6 B5 B6
3Y2 3Y3
7Y2 7Y3 7Y4
3Y4
A4 2OE C5 2A1 C6 2A2 D5 2A3 2A4 D6 D1 D2 C2 C1 2Y1 4OE
H3
6OE G2 4Y1 G1 H1 H2
J4 8OE L5 L2 6Y1
T3
4A1
G5 G6
6A1 L6 6A2 M5 6A3 6A4 M6 M1 M2 L1
R5 8A1 R6 8A2 T6 8A3 8A4 T5
R2 R1 T1 T2
8Y1
2Y2 2Y3
4A2 H6 4A3 4A4 H5
4Y2 4Y3
6Y2 6Y3 6Y4
8Y2 8Y3 8Y4
2Y4
4Y4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c)2000 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4906/1
IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6 2A2
1A2
1A4
2A4
3A2
3A4
4A2
4A3
5A2
5A4
6A2
6A4
7A2
7A4
8A2
8A3
5
1A1
1A3
2A1
2A3
3A1
3A3
4A1
4A4
5A1
5A3
6A1
6A3
7A1
7A3
8A1
8A4
4 2OE
GND GND
1Y3
VCC VCC
GND
GND
VCC VCC
GND GND
3OE
6OE
GND GND
5Y3
VCC VCC
GND GND
GND GND
VCC VCC
7Y3
GND GND
7OE
3
1OE
GND
2Y3
GND
4OE
5OE
8OE
2
1Y1
2Y1
3Y1
3Y3
4Y1
4Y4
5Y1
6Y1
6Y3
7Y1
8Y1
8Y4
1
1Y2 A
1Y4 B
2Y2 C
2Y4 D
3Y2 E
3Y4 F
4Y2 G
4Y3 H
5Y2 J
5Y4 K
6Y2 L
6Y4 M
7Y2 N
7Y4 P
8Y2 R
8Y3 T
LFBGA TOPVIEW
96 BALL LFBGA PACKAGE ATTRIBUTES
1.5mm Max. 1.4mm Nom. 1.3mm Min.
0.8mm
6 5 4 3 2 1 A B C D E F G H J K L M N P R T
TOP VIEW
A 1 2 3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
5.5mm 4 5 6
13.5mm
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IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT IIK IOK ICC ISS Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100
Unit V V C mA mA mA mA
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1. As applicable to the device type.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
PIN DESCRIPTION
Pin Names xOE xAx xYx Data Inputs
(1)
FUNCTION TABLE (EACH 4-BIT BUFFER)(1)
Description Inputs xOE L L H
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
Outputs xAx H L X xYx H L Z
3-State Output Enable Inputs (Active LOW) 3-State Outputs
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
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IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance per Driver Outputs enabled Power Dissipation Capacitance per Driver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 32 8 VCC = 3.3V 0.3V Typical 38 10 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) Parameter Propagation Delay xAx to xYx Output Enable Time xOE to xYx Output Disable Time xOE to xYx Output Skew(2) -- -- -- -- -- 500 ps 1 5.2 -- 4.6 1 4.1 ns 1 5.7 -- 5.4 1 4.4 ns Min. 1 Max. 3.7 VCC = 2.7V Min. -- Max. 3.6 VCC = 3.3V 0.3V Min. 1 Max. 3 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND
VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VIN D.U.T. RT
VOUT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
VT
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALVC Link
Pulse Width
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX ALVC IDT Temp. Range X Bus-Hold XX Family XX XXXX Device Type Package
BF 244
Low Profile Fine Pitch Ball Grid Array 32-Bit Buffer/Driver with 3-State Outputs
32 H 74
32-Bit Bus Density, 24mA Bus-Hold -40C to +85C
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